1. Field of the Invention
The present invention relates generally to interconnect structures for integrated circuits and, more particularly, to a local interconnect manufactured with fewer mask steps for random access memory circuits.
2. Background of the Related Art
Random access memories, in both dynamic (DRAM) and static (SRAM) forms, are complex integrated circuits that have become commodity items in the electronics industry. Despite their complexity, price competition requires that memory designs be inexpensive to manufacture while at the same time maintaining high performance and high reliability. For example, it can be a significant advantage if a memory design can eliminate one or more processing steps. In particular, many integrated circuits use multiple layers of patterned metallization to provide interconnect wiring between devices. Each layer of metallization increases cost significantly while creating additional reliability concerns created by the additional processing. Hence, it is typically desirable to minimize the number metallization layers required to implement a design.
The present invention may be directed to one or more of the problems set forth above.
In accordance with one aspect of the present invention, there is provided a method of manufacturing an interconnection for an integrated circuit. The method includes the steps of: (a) disposing a layer of dielectric material on a substrate; (b) forming a mask over the dielectric material, the mask having a first window portion and a second window portion; (c) removing a portion of the layer of dielectric material under the first window portion to form a first cavity portion and removing a portion of the layer of dielectric material under the second window portion to form a second cavity portion; (d) disposing a layer of masking material into the first cavity portion and the second cavity portion, the layer of masking material completely filling the first cavity portion and partially filling the second cavity portion; (e) removing a portion of the masking material to expose a bottom portion of the second cavity portion; (f) removing a portion of the layer of dielectric material under the exposed bottom portion of the second cavity portion to extend the second cavity portion; and (g) filling the first cavity portion and the second cavity portion with conductive material.
In accordance with another aspect of the present invention, there is provided a method of manufacturing an interconnection for an integrated circuit. The method includes the steps of: (a) disposing a layer of dielectric material on a substrate; (b) forming a mask over the dielectric material, the mask having a first window portion and a second window portion; (c) removing a portion of the layer of dielectric material under the first window portion to form a first cavity portion and removing a portion of the layer of dielectric material under the second window portion to form a second cavity portion; (d) disposing a layer of masking material into the first cavity portion and the second cavity portion, the layer of masking material completely filling the first cavity portion and partially filling the second cavity portion; (e) removing a portion of the masking material to expose a bottom portion of the second cavity portion; (f) removing a portion of the layer of dielectric material under the exposed bottom portion of the second cavity portion to extend the second cavity portion; (g) removing the masking material; and (h) filling the first cavity portion and the second cavity portion with conductive material.
In accordance with still another aspect of the present invention, there is provided a method of manufacturing an interconnection for an integrated circuit. The method includes the steps of: (a) disposing a layer of dielectric material on a substrate; (b) forming a mask over the dielectric material, the mask having a first window portion and a second window portion; (c) removing a portion of the layer of dielectric material under the first window portion to form a first cavity portion and removing a portion of the layer of dielectric material under the second window portion to form a second cavity portion; (d) disposing a layer of conductive material into the first cavity portion and the second cavity portion, the layer of masking material completely filling the first cavity portion and partially filling the second cavity portion; (e) removing a portion of the conductive material to expose a bottom portion of the second cavity portion; (f) removing a portion of the layer of dielectric material under the exposed bottom portion of the second cavity portion to extend the second cavity portion; and (g) filling the second cavity portion with conductive material.
In accordance with yet another aspect of the present invention, there is provided a method of manufacturing an interconnection for an integrated circuit. The method includes the steps of: (a) disposing a layer of dielectric material on a substrate; (b) forming a mask over the dielectric material, the mask having a window therein, the window having an elongated portion and a widened portion; (c) removing a portion of the layer of dielectric material under the window to form a cavity having an elongated portion and a widened portion; (d) disposing a layer of masking material into the cavity, the layer of masking material completely filling the elongated portion of the cavity and partially filling the widened portion of the cavity; (e) removing a portion of the masking material to expose a bottom portion of the widened portion of the cavity; (f) removing a portion of the layer of dielectric material under the exposed bottom portion of the widened portion of the cavity; and (g) filling the cavity with conductive material.
In accordance with a further aspect of the present invention, there is provided a method of manufacturing an interconnection for an integrated circuit. The method includes the steps of: (a) disposing a layer of dielectric material on a substrate; (b) forming a mask over the dielectric material, the mask having a window therein, the window having an elongated portion and a widened portion; (c) removing a portion of the layer of dielectric material under the window to form a cavity having an elongated portion and a widened portion; (d) disposing a layer of masking material into the cavity, the layer of masking material completely filling the elongated portion of the cavity and partially filling the widened portion of the cavity; (e) removing a portion of the masking material to form a spacer in the widened portion of the cavity and to expose a bottom portion of the widened portion of the cavity; (f) using an etchant to remove a portion of the layer of dielectric material under the exposed bottom portion of the widened portion of the cavity, the etchant removing the spacer at a slower rate than the layer of dielectric material under the exposed bottom portion of the widened portion of the cavity; and (g) filling the cavity with conductive material.
In accordance with a still further aspect of the present invention, there is provided a method of coupling a gate of a first transistor to an active region of a second transistor. The method includes the steps of: (a) disposing a layer of dielectric material over the first transistor and the second transistor; (b) forming a mask over the dielectric material, the mask having a window therein, the window having an elongated portion extending between the first transistor and the second transistor, and the window having a first widened portion over the gate of the first transistor and a second widened portion over the active region of the second transistor; (c) removing a portion of the layer of dielectric material under the window to form a cavity having an elongated portion, a first widened portion, and a second widened portion; (d) disposing a layer of masking material into the cavity, the layer of masking material completely filling the elongated portion of the cavity and partially filling the first and second widened portions of the cavity; (e) removing a portion of the masking material to expose a bottom portion of the first widened portion of the cavity and to expose a bottom portion of the second widened portion of the cavity; (f) removing a portion of the layer of dielectric material under the exposed bottom portion of the first widened portion of the cavity to extend the first widened portion of the cavity to the gate of the first transistor, and removing a portion of the layer of dielectric material under the exposed bottom portion of the second widened portion of the cavity to extend the second widened portion of the cavity to the active region of the second transistor; and (g) filling the cavity with conductive material.
In accordance with a yet further aspect of the present invention, there is provided a method of coupling a terminal of a first transistor to a terminal of a second transistor. The method includes the steps of: (a) disposing a layer of dielectric material over the first transistor and the second transistor; (b) forming a mask over the dielectric material, the mask having a window therein, the window having an elongated portion extending between the first transistor and the second transistor, and the window having a first widened portion over the terminal of the first transistor and a second widened portion over the terminal of the second transistor; (c) removing a portion of the layer of dielectric material under the window to form a cavity having an elongated portion, a first widened portion, and a second widened portion; (d) disposing a layer of masking material into the cavity, the layer of masking material completely filling the elongated portion of the cavity and partially filling the first and second widened portions of the cavity; (e) removing a portion of the masking material to expose a bottom portion of the first widened portion of the cavity and to expose a bottom portion of the second widened portion of the cavity; (f) removing a portion of the layer of dielectric material under the exposed bottom portion of the first widened portion of the cavity to extend the first widened portion of the cavity to the terminal of the first transistor, and removing a portion of the layer of dielectric material under the exposed bottom portion of the second widened portion of the cavity to extend the second widened portion of the cavity to the terminal of the second transistor; and (g) filling the cavity with conductive material.
In accordance with an even further aspect of the present invention, there is provided a transistor interconnection between a first transistor and a second transistor. The first transistor has a first active region bisected by a first gate electrode, and the second transistor has a second active region bisected by a second gate electrode. The interconnection includes a first conductive contact formed in a dielectric layer covering the first and second transistors. The first contact is positioned over and coupled to the first active region of the first transistor. A second conductive contact is formed in the dielectric layer. The second contact is positioned over and coupled to the second gate electrode in the second active region. A conductive runner is formed in the dielectric layer. The conductive runner is coupled to the first conductive contact and to the second conductive contact. The conductive runner extends therebetween over a portion of the first active region and over a portion of the second active region.